The present invention relates to a multi-stage high-frequency power amplifier circuit with a plurality of cascaded semiconductor amplifier devices and technology that is useful when applied to wireless communication devices such as cellular phones incorporating a high-frequency power amplifier circuit, and more particularly to a high-frequency power amplifier circuit capable of obtaining output with desired characteristics, independent of variations in semiconductor amplifier device characteristics.
The transmission output stage of car phones, cellular phones, and other wireless communication devices (mobile communication devices), as shown in FIG. 1, includes a multi-stage high-frequency power amplifier circuit with cascaded semiconductor amplifier devices Q1, Q2, and Q3 made of MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), GaAs-MESFETs (Metal Semiconductor Field-Effect Transistors), or other applicable kinds of transistors. The high-frequency power amplifier circuit shown in FIG. 1 generally includes a discrete last-stage semiconductor amplifier device Q3 (such as an output power MOSFET), and preceding-stage semiconductor amplifier devices Q1 and Q2 and a bias circuit BIAS that are integrated onto a single semiconductor chip as a semiconductor integrated circuit. The combination of this discrete semiconductor amplifier device part and a semiconductor integrated circuit including a bias circuit, together with capacitive elements and other circuit elements will be referred to as a high-frequency power amplifier module or just as a module hereinafter.
In general, a cellular phone system is configured to change its output (transmission power) in different communication environments according to power-level command signals from a base station, so as not to interfere with other cellular phones. For example, a high-frequency power amplifier module in the transmission output stage of cellular phones adopting the U.S. 900-MHz band standard system or the European GSM (Global System for Mobile Communications) system is configured so that the gate bias voltages of the output power MOSFETs Q1 to Q3 are controlled by the output voltage Vapc of an Automatic Power Control (APC) to produce the output power required for communication.
Conventionally, the gate bias voltages of the output power MOSFETs are generated by using a bias circuit BIAS consisting of resistance dividers as shown in FIG. 1, in which the output voltage Vapc of the APC circuit is divided by the ratios of paired resistances R11 and R12, R21 and R22, and R31 and R32 to generate gate bias voltages Vg1, Vg2, and Vg3 (see, for example, Unexamined Japanese Patent Publication No. Hei 11(1999)-150483).
Some conventional systems, as shown in FIG. 2, use a bias circuit that is configured with a plurality of resistances R1 to R4 connected in series with a MOSFET Qd that functions as a diode, forming a resistive voltage in which the ratio of the resistance values is adjusted so that the maximum output power can be obtained when Vapc is in the high neighborhood of 2 V, generating the gate bias voltages Vg1, Vg2, and Vg3 of the output power MOSFETs in each stage (see, for example, Unexamined Japanese Patent Publication No. 2001-102881).
As described above, all of the conventional gate bias circuits above apply bias voltages generated by dividing the output voltage Vapc of the APC circuit to the gates of the output power MOSFETs.
Output power MOSFETs show variations in threshold voltages due to manufacturing process variations and temperature changes. In addition, the last-stage MOSFET Q3 among the output power MOSFETs, in particular, is often a discrete part. Therefore, the last-stage MOSFET Q3 and preceding-stage MOSFETs Q1 and Q2 differ in regard to the variations in the threshold voltage. More specifically, the gate voltage-drain current characteristics of the output power MOSFETs are different from each other.
In such a high-frequency power amplifier module configured with output power MOSFETs having different variations in their threshold voltages, if a gate bias voltage that is generated by dividing the output voltage Vapc of the APC circuit according to the ratio of resistances is applied to the gate terminals of the output power MOSFETs, the output characteristic of the high-frequency power amplifier circuit may deviate greatly from a desired characteristic. As a result, a module with a bias circuit that generates gate bias voltage by dividing resistances requires fine tuning of the resistance values making up the bias circuit; this obviously creates a problem in that extra trimming tasks or trimming resistors are required.
Accordingly, an object of the present invention is to provide a high-frequency power amplifier circuit capable of obtaining desired characteristics without trimming the values of resistors making up the bias circuit.
Another object of the present invention is to provide a high-frequency power amplifier circuit with better output controllability.
Another object of the present invention is to provide a high-frequency power amplifier circuit capable of efficiently obtaining higher output with lower power consumption.
The aforementioned and other objects and new features of the present invention will become clear from the description in this specification when read with reference to the attached drawings.
The outline of a typical mode of practicing the invention disclosed herein will be described below.
In a multi-stage high-frequency power amplifier circuit with a plurality of cascaded output semiconductor amplifier devices Q1, Q2, and Q3, the invention typically provides semiconductor amplifier devices Q11, Q12, and Q13 connected to the plurality of output semiconductor amplifier devices to form current mirror circuits respectively, causing electric currents I11, I12, and I13 changing with given characteristics according to control voltage to flow into the semiconductor amplifier devices and driving the plurality of output semiconductor amplifier devices with the currents.
The method described above drives the output semiconductor amplifier devices with currents having given characteristics, thereby making it possible to obtain a high-frequency power amplifier circuit with output characteristics not sensitive to possible variations in the threshold voltages and other characteristics of the output semiconductor amplifier devices.
The semiconductor amplifier devices are preferably field effect transistors, and the given characteristics are their gate voltage-drain current characteristics. Since the drain current of a field effect transistor is proportional to the square of the gate voltage, the control voltage can reduce the rate of change of the output in the vicinity of the threshold voltage of the field effect transistor and increase the rate of change of the output by increasing itself, thereby making it possible to achieve higher output controllability and larger output power.
According to another aspect of the invention disclosed herein, in a high-frequency power amplifier circuit having a multi-stage output circuit with a plurality of cascaded semiconductor amplifier devices Q1, Q2, and Q3 and a bias circuit that drives the semiconductor amplifier devices responsive to a control voltage, the invention provides semiconductor amplifier devices Q11, Q12, and Q13 that are connected to the plurality of output semiconductor amplifier devices so as to form current mirror circuits; the bias circuit has a voltage-to-current converter 10, a first resistance R1 that converts currents I1 and I3 supplied from the voltage-to-current converter, a first constant-current source 31, and a first semiconductor amplifier device Q32 connected in series thereto; also included is a control voltage generator 30 that generates a voltage equal to the threshold voltage of the first semiconductor amplifier device; a second semiconductor amplifier device Q21 (Q31) generates current according to a combination of the voltage generated by the control voltage generator and the voltage converted by the first resistance; and currents I11, I12, and I13 with the same characteristic as that of current I21 flowing through the second semiconductor amplifier device are passed through the semiconductor amplifier devices connected to the plurality of output semiconductor amplifier devices in pair respectively so as to form the current mirror circuits to drive the plurality of output semiconductor amplifier devices.
Preferably, the control voltage generator has a voltage follower 33 including a first differential circuit that receives a voltage equal to the threshold voltage of the first semiconductor amplifier device; the first resistance R1 is connected to the output terminal of the voltage follower; and currents I1 and I3 fed from the voltage-to-current converter via the first resistance are caused to flow through the voltage follower. This enables the voltage follower, which has small output impedance, to sink sufficient currents I1 and I3 supplied from the voltage-to-current converter and generate a voltage proportional to the currents I1 and I3 supplied from the voltage-to-current converter through the first resistance to be applied to the control terminal of the second semiconductor amplifier device to produce current.
More preferably, second constant-current sources 21a and 21c that are connected to the control terminals of the second semiconductor amplifier devices and sink current supplied from the voltage-to-current converter are provided. This can produce an initial control voltage at which the current passing through the second semiconductor amplifier devices starts to change, thereby making it easier to obtain a desired current characteristic.
The first constant-current source 31 is configured to include a second differential circuit 312 receiving a constant voltage as an input from a band gap reference circuit 311 that generates a constant voltage and a third semiconductor amplifier device Q30 that carries constant current from the output of the second differential circuit. This can make the current characteristic of the first output semiconductor amplifier device constant regardless of variations in the power source voltage.
In addition, the second differential circuit 312 has its output fed back to the other input through a circuit including an amplifier device Q44 and a second resistance R4. This feedback causes the second differential circuit to output a voltage Vc1 proportional to the constant voltage Vref from the output terminal. The third semiconductor amplifier device Q30 forms a current mirror with the amplifier device Q44 to pass a current responsive to the value of the second resistance R4 as a constant current I4. The second resistance R4 is constituted by an external device. Since an external device can be provided with higher accuracy than a device integrated on a chip, using it can improve operation accuracy of the circuit.
In addition, the second constant-current source 21a (21c) is configured to include a third differential circuit 321 that receives a constant voltage (Vref) as an input from the band gap reference circuit 311, which generates a constant voltage with little dependecy on the power source voltage, and a fourth semiconductor amplifier device Q31 that carries constant current responsive to the output Vc2 of the third differential circuit. This makes it possible to provide the first output semiconductor amplifier device with a constant current characteristic independent of variations in the power source voltage.
The output of the third differential circuit 321 is fed back to the other input via a circuit including an amplifier device Q45 and a third resistance R5. This feedback causes the third differential circuit to output a voltage Vc2 proportional to the constant voltage Vref from the output terminal. The fourth semiconductor amplifier device Q31 constitutes a current mirror with the amplifier device Q45 and is configured to pass current responsive to the value of the third resistance R5 as a constant current I5a (I5c); the third resistance R5 is formed integrally with the first to fourth semiconductor amplifier devices in the same semiconductor chip. When the output currents I1 and I3 vary due to manufacturing process variations in the value of the resistance R2 provided in the voltage-to-current converter 10, this configuration causes the same variation in the value of the third resistance R5 as in the resistance R2 in the voltage-to-current converter, which causes a current I5a (I5c) to change, thereby enabling the changes in the output currents I1 and I3 to be canceled.
Furthermore, the first resistance, the second semiconductor amplifier device, and the second current source are provided for each of the plurality of the output semiconductor amplifier devices; the resistance value of the first resistance and the current value of the second current source are set to mutually differing values. This enables separate control with desired characteristics of the plurality of output semiconductor amplifier devices, thereby making it possible to achieve a high-frequency power amplifier circuit with better output controllability and capable of efficiently obtaining higher output with lower power consumption.